Data processing apparatus and system and method for controlling memory access

ABSTRACT

A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements.

FIELD OF THE INVENTION

The present invention relates to a data processor apparatus, and inparticular to a system and method for controlling access to a memorywhich is shared by two or more data processors or other devices.

BACKGROUND OF THE INVENTION

In a typical computer system having multiple computer processor units(CPUs) which require access to a common memory, the CPUs and memory areconnected to a data communication bus for shared memory access. Anexample of a multi-CPU system is shown in FIG. 1. The system 1 includesa number of microprocessors 3, 5 and other devices such as a DirectMemory Access (DMA) device 7 and an input/output (I/O) device 9connected to a data communication bus 11, which is also connected to anumber of shared memory blocks 13, 15 by respective memory interfaceunits (MIU) 17, 19. One problem with this implementation is that onlyone memory can be accessed by only one microprocessor or other device atany one time through the data communication bus, which often leads to abottle neck or congestion in data transfer. For example, ifmicroprocessors 3, 5 both require access to a memory at the same time,and one of the microprocessors has priority over the other, themicroprocessor having lower priority has to wait until memory access bythe higher priority microprocessor is complete. This problem becomesgreater as the number of devices connected to the data communication busincreases, so that, for example, access waiting times for other devicessuch as the DMA and input/output devices become significantly large.

Another form of data processor is the single-instruction-multiple-data(SIMD) processor, which has multiple processor units each having its ownassociated memory space. The processor units are simple processors,unable to fetch or interpret instructions, and are controlled by asingle control unit, so that the processor units act as slaves to thecontrol unit, performing at its request, arithmatic-logic operations. Atypical SIMD architecture is depicted in FIG. 2. The data processor 21has a number of processing units 23, 25 each coupled to an associatedmemory 27, 29. The data processor has a control unit (not shown) forcontrolling the processing units in parallel via a data communicationbus 33 and other devices such as a DMA 35 and an input/output device 37,which are also connected to the data communication bus. One advantage ofthis system is that more memory and processor units can be easily addedto the computer. However, a disadvantage of this system is that when aprocessor unit requires access to the memory space of another processorunit, the transfer of data is managed by the control unit, whichtherefore consumes control unit processing time or cycles, and duringthe time data is being moved around, the processor units remain idle.

Another example of a SIMD processor is described in U.S. Pat. No.5,956,274 issued on 21 Sep., 1999 to Duncan G. Elliot, et al, and isshown schematically in FIG. 3. In this architecture, the processingunits 33 are placed within the memory, there being one processor unitper column of storage elements, each processor unit being directlycoupled to the sense amplifier of each column, and whose output iscoupled to the memory column decoder. While this architecture provides alarge number of processor units, each tightly coupled to its own memoryspace, when the microprocessor requires access to memory, the processorelements must remain idle. A further disadvantage of this architectureis that the memory must be designed specifically to incorporate theprocessing elements.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided adata processor apparatus comprising a memory having a plurality ofstorage elements arranged in a plurality of columns, a plurality ofcolumn decoders, a plurality of memory ports coupled to the decoders forat least one of outputting data from the memory and receiving data forthe memory, and a plurality of processing elements, wherein each of theplurality of memory ports is coupleable to at least a respective one ofthe plurality of processor elements, such that each processor element iscapable of accessing at least one column of storage elements.

In this arrangement, the processor elements are coupleable to theexternal interface ports of the memory, rather than being embedded inthe memory between the sense amplifiers and column decoder.Advantageously, this architecture enables a parallel data processor tobe realized having a plurality of processing elements each having accessto its own portion of memory, but without the requirement for knowledgeof the internal memory structure, thereby considerably simplifyingdesign, reducing design time, and offering designers the flexibility ofusing any suitable memory for the intended application.

In one embodiment, the data processor apparatus includes switch meansbetween at least one, and preferably each of the memory ports, and atleast one, and preferably each of the processor elements, forselectively coupling and decoupling the memory port(s) to and from theprocessor element(s). Advantageously, this arrangement enables theprocessor elements to be decoupled from the memory, so that the memorycan be accessed by another device. At the same time, this allows theprocessor elements to continue to perform operations, for exampleprocessing data which was previously read from the memory. In oneembodiment, at least one storage element is provided for at least oneand preferably each processor element for storing data read from thememory before being processed by the processing elements. In oneembodiment, the storage elements can be decoupled from the memory, againto enable the memory to be accessed by another device while allowing theprocessor elements to process data stored in the storage element(s).

According to another aspect of the present invention, there is provideda data processor apparatus comprising a memory having a plurality ofmemory ports for at least one of outputting data from the memory andreceiving data for the memory, a processor coupleable to the memoryports, and a data bus coupleable to the memory ports, and a memoryaccess controller for selectively coupling and decoupling the data busto and from the memory ports.

Advantageously, this arrangement allows the data bus to be decoupledfrom the memory, so that the data bus can be used to transfer data, forexample between different devices connected to the data bus, while thememory is being accessed by the processor.

According to another aspect of the present invention, there is provideda memory device comprising a memory having a plurality of memory portsfor at least one of outputting data from the memory and receiving datafor the memory, first and second data buses, each being coupleable tothe memory ports, and memory access control means for selectivelycoupling one of the first and second data buses to the memory ports.

Advantageously, this arrangement enables each of the data buses to bedecoupled from the memory so that the decoupled data bus can continue tobe used by other devices, while the other data bus is coupled to thememory.

According to another aspect of the present invention, there is provideda memory device comprising a memory having a plurality of memory portsfor at least one of outputting data from the memory and receiving datafor the memory, a data bus having a plurality of bus lines, wherein thenumber of bus lines is different to the number of memory ports, anddecoding means between the memory ports and the data bus for one ofcoupling selected ones of the memory ports to the bus lines, if thenumber of memory ports exceeds the number of bus lines, and couplingselected ones of the bus lines to the memory ports, if the number of buslines exceeds the number of memory ports.

Advantageously, this arrangement provides a decoder coupled between thememory ports and a data bus having a different number of serial bitlines to the number of memory ports, and controls the selection of whichmemory ports are coupled to which serial bus lines to enable any size ofdata bus full access to any size of memory, and vice versa.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of embodiments of the present invention will now be describedwith reference to the drawings, in which:—

FIG. 1 shows a block diagram of a multi-processor computer architectureaccording to the prior art;

FIG. 2 shows a block diagram of a single-instruction-multiple-data(SIMD) processor architecture, according to the prior art;

FIG. 3 shows a block diagram of another example of a SIMD processorarchitecture, according to the prior art;

FIG. 4 shows a block diagram of a data processor apparatus according toan embodiment of the present invention;

FIG. 5 shows a diagram of a data processor apparatus, according toanother embodiment of the present invention;

FIG. 6 shows a diagram of a memory access controller according to anembodiment of the present invention;

FIG. 7 shows an example of a memory access controller according toanother embodiment of the present invention;

FIG. 8 shows an example of a memory access controller according toanother embodiment of the present invention, and

FIG. 9 shows a table of memory allocation for data received on twodifferent buses, according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 4 shows a data processor according to an embodiment of the presentinvention. The data processor 101 comprises a memory 103, e.g. a randomaccess memory, having a plurality of storage elements 105 arranged inrows 107 and columns 109 (only a few of which are shown for clarity).The memory 103 includes a row decoder (or selector) 111, a plurality ofsense amplifiers 113, one for each column 109 of storage elements, and aplurality of column decoders (or selectors) 115. Each sense amplifier113 is arranged to amplify the signal either received on the memorycolumn line to which it is connected (in the case of a memory read), orto amplify a received signal for outputting onto the column line (in thecase of a memory write). Each column selector 115 has a plurality ofinput/output ports 117, one being connected to a respective input/outputport of the sense amplifiers. In this embodiment, each column selector115 is arranged to select from one of eight columns 109 of memory and toconnect the selected column via a respective sense amplifier 113 to anI/O port 119. The memory columns, sense amplifiers and column selectorsmay extend laterally to include any number of memory columns, associatedsense amplifiers and column selectors, to provide the required size ofmemory.

In one embodiment, the memory 103 may comprise a memory bank containinga plurality of memory modules.

The data processor 101 further includes a plurality of processingelements 121 each having an I/O port 123 connected to a respective I/Oport 119 of the respective column selectors 115. In this embodiment, theprocessor elements are arranged in a one dimensional array, and there isone processor element per column selector 115, although in otherembodiments, the data processor 101 may include a processor block havingtwo or more processor elements coupleable to each memory I/O port.

Advantageously, the processor architecture of the present embodiment, inwhich each processor element 121 is coupleable to a memory I/O portsubstantially simplifies the design process of integrating processorelements with a memory, e.g. RAM. One of the problems associated withthe architecture described in U.S. Pat. No. 5,956,274 (Elliot et al) isthat by placing the processing elements between the sense amplifiers andthe memory decoding circuits, access to the memory design is required.However, most high performance memory structure designs are strictlyguarded company secrets, and therefore the only companies that are ableto add structures within the memory column decoding circuits are thememory vendors themselves, and processor design is normally outsidetheir scope of expertise, or would require too much time. In contrast,the present architecture allows any compileable memory structure to beused for the data processor, since the processor elements are coupled tothe memory I/O ports, rather than to the sense amplifiers, and thereforedetailed knowledge concerning the internal memory structure is notrequired.

In the present embodiment, the connection between each processor element117 and memory I/O port 119 can be regarded as a one bit line of aparallel data bus 127, which may have a width of any number of bits,e.g. 16, 32, 64, 128, 192, 256 . . . etc., or any other number.

FIG. 5 shows a data processor according to another embodiment of thepresent invention. The data processor 201 comprises a memory 203, aparallel processing engine 205; an array controller 207, a memoryarbitration unit 209, a data communication bus 211, a microprocessor 213and one or more other devices 215, 217. The microprocessor 213 and theother devices 215, 217 are connected to the data communication bus 211.The memory arbitration unit 209 is coupled both to the datacommunication bus 211 and to the parallel processing engine 205, and isarranged to control access to the memory 203 by the microprocessor 213or other device 215, 217 connected to the data communication bus 211, orby the parallel processing engine 205. The array controller 207 is alsocoupled to the data communication bus 211 and is arranged to control theparallel processing engine 205. The memory 203 has a plurality of I/Oports 219 (indicated schematically by the row of arrows between thememory 203 and the memory arbitration unit 209), which are coupleablethrough the memory arbitration unit to I/O ports 223 of the parallelprocessing engine 205 via a data bus 227.

In one embodiment, the memory arbitration unit 209 is adapted toselectively permit data transfer between the memory and the datacommunication bus 211, or between the memory 203 and the parallelprocessing engine 205, where the data communication bus 211, whichenables data communication to and from the microprocessor 213 (and otherdevices 215, 217), has a different number of single bit bus lines to thedata bus 227, which enables data to be transferred between the memory203 and the parallel processing engine 205.

In another embodiment, the memory arbitration unit 209 is adapted tode-couple the parallel processing engine 205 from the memory 203, and toenable the processing engine 205 to continue to process data while atthe same time permitting a device 213, 215, 217 coupled to the datacommunication bus 211 to access the memory 203. Embodiments of thearbitration unit 209 will now be described with reference to FIGS. 6, 7and 8.

Referring to FIG. 6, a data processing apparatus 301 comprises a memory303, a first processor 305 and one or more optional peripheral devices307, connected to a first data bus 309. The processing apparatus 301further includes a second processor 311 and, optionally, one or moreadditional peripheral devices 313 connected to a second datacommunication bus 315. In this embodiment, the second data communicationbus 315 has a greater number of single bit lines than the firstcommunication bus 309, and in the particular embodiment shown in FIG. 5,the first data communication bus has a single bit width of 32 (bitlines) and the second communication bus 315 has a single bit width of192 (bit lines), although in other embodiments the first and secondcommunication buses may have any other number of bit lines.

A memory arbitration unit 317 includes a third data bus 319 having thesame number of single bit lines (i.e. bit width) as the second datacommunication bus 315 (in this particular embodiment 192 bit lines),each coupled to an I/O port of the memory 303. The memory arbitrationunit (MAU) 317 further includes a decoder 321, one side of which iscoupled to the third communication bus 319 and the other side of thedecoder being switchably coupled to the first communication bus 309 viaa first switching unit 323. The third bus 319 of the MAU 317 is alsoswitchably coupled to the second communication bus 315 via a secondswitching unit 325.

The decoder 321 is capable of connecting each of the single bit lines ofthe first communication bus 309 to a selected single bit line of thethird communication bus 319. For example, in read or write memoryaccess, the decoder 321 may be controlled to connect the 32 bit lines ofthe first communication bus to the first 32 I/O ports of the memory viathe first 32 of the 192 bit lines of the third communication bus 319,which allows, for example 4 bytes of data to be written to, or read frommemory in parallel. In a subsequent operation, the decoder 321 may becontrolled to connect each of the 32 bit lines of the firstcommunication bus 309 to the next 32 I/O ports of the memory 303 via thenext 32 bit lines of the 192 bit communication bus 319, therebypermitting a subsequent 4 bytes of data to be read from or written tothe memory 303. The first switching unit 323 may comprise any suitableswitching means which enables the first communication bus 309 to beswitchably connected to and decoupled from the MAU bus 319. Preferably,the switching unit 323 is switchable between a closed position and anopen (i.e. neutral or floating) e.g. tri-state position. In oneembodiment, the switching unit may comprise a plurality of tri-stateablebuffers, one connected in each single bit line between the decoder 321and the first data communication bus 309.

The second switching unit 325 may also comprise any suitable means whichswitchably connects and decouples the second data communication bus 315to and from the MAU data communication bus 319. Preferably, the secondswitching unit is switchable between closed and open (i.e. neutral orfloating) positions, and, as for the first switching unit 323, maycomprise a plurality of switching elements, such as a tri-stateablebuffer, one connected in each bit line between the second datacommunication bus 315 and the MAU data bus 319.

The MAU 317 has a memory access controller 326 which controls access tothe memory 303 by the device(s) coupled to the first and second datacommunication buses. The memory access controller may be arranged toarbitrate memory access between devices coupled to the same datacommunication bus 309, 311 and to arbitrate between devices coupled todifferent data communication buses 309, 315. In operation, the memoryaccess controller may receive memory access requests from the variousdevices and may be arranged to control the connectivity between eachdevice and memory based on predetermined rules, which may includedifferent priorities assigned to different devices and round robinmemory accesses for devices having equal priority. The memory accesscontroller may be arranged to control the decoder 321, the firstswitching unit 323 to selectively connect and decouple the first datacommunication bus 309 to and from the memory 303, and/or the secondswitching unit 325 to selectively connect and decouple the second datacommunication bus 315 to and from the memory 303.

Advantageously, the memory arbitration unit 317 allows data buses ofdifferent widths or capacity (i.e. having different numbers of singlebit lines) to be selectively coupled to a memory, and therefore allows amemory to be shared between devices which handle different length words.The MAU 317 also enables a selected communication bus to be decoupledfrom the memory, so that the decoupled bus can continue to be used, forexample, to transfer data between devices connected to the same bus.

In one embodiment, the second processor 311 may include one or moreregisters for receiving data from the memory 303 prior to processing.Advantageously, this enables the processor to process data and at thesame time the memory 303 to be accessed by another device, for exampleby the first processor 305, or by another peripheral device 307, 313.For example, while the second processor 311 is processing data, theresult of a previous calculation by the second processor 311 stored inmemory 303 may be output via the first data communication bus 309 to adevice connected thereto, for example an output device. The secondprocessor 311 may comprise a parallel processing engine containing aplurality of processor elements, similar to that described above withreference to FIGS. 4 and 5. The processing engine may be arranged toperform parallel processing on a two-dimensional array of datarepresentative of an image. While a calculation is being performed, forexample on one image frame, the memory 303 may be accessed to output aprevious image frame, calculated by the two-dimensional array processorand written to the memory 303. In another embodiment, the MAU 317 may beadapted to temporarily store data from the memory 303 prior toprocessing by the second processor 311, which again may permit thememory 303 to be accessed by another device while the processor accessesand/or processes the stored data. An example of a memory arbitrationunit having a buffer or memory is shown in FIG. 7.

FIG. 7 shows a data processor apparatus 301, which is similar to thatshown in FIG. 5, and like parts are designated by the same referencenumerals. The data processor has a memory 303, a first processor 305 andoptionally additional peripheral devices 307 connected to a data bus309. The memory arbitration unit 317 includes a data communication bus319, a decoder 321 and a switching unit 323, and the description ofthese components given above in connection with the embodiment of FIG. 6applies equally to the embodiment of FIG. 7. The main difference betweenthe embodiments of FIGS. 6 and 7 is that, in the embodiment of FIG. 7,the memory arbitration unit 317 includes a plurality of register units327, one being connected to each single bit line of the MAU datacommunication bus 319. In this embodiment, each register unit 327 hasfirst and second registers 329, 331 which are separately coupleable to arespective single bit line of the bus 319, and a two to one selectorswitch 333 for selectively connecting the output of one of the first andsecond registers to a single bit line 335, each of which is connected toan input of the second processor 311. The second processor may comprisea parallel processing engine, for example having a plurality ofprocessing elements, each of which is capable of processing datareceived on a single bit line to which it is connected. For example, theparallel processing engine may be similar to that described above inconnection with FIGS. 4, 5 or 6.

In this embodiment, the provision of register units 327 allows data tobe written from the memory 303 into the registers for processing by theprocessor 311. Writing to the first and second registers of the registerunits 327 may be controlled by a write enable signal applied to theregisters, as required. The registers also provide a means fordecoupling the MAU bus 319 from the registers and the second processor311, by disabling the write enable control signal. Thus, once data hasbeen written to one or more of the first and second registers of eachunit 327, the registers can be decoupled from the MAU bus 319, forexample, by disabling the write enable control signal, so that thememory 303 can be accessed by another device, for example connected tothe data communication bus 309. At the same time, data stored in one ormore of the first and second registers can be accessed and processed bythe second processor 311. In addition to controlling the switchingoperations of the decoder 321 and the switching unit 323, the memoryaccess controller 326 may also be arranged to control write operationsinto each of the first and second registers 329, 331, and readoperations from one or more of the registers into the second processor311.

In other embodiments, the register units 327 may have any number (i.e.one or more than one) registers, and the selector switch 333 may beomitted, for example, if the register unit contains a single register,and may be sized to switchably connect any of the registers to thesecond processor, if the register unit contains two or more registers.

Advantageously, the more registers that are provided per single bitline, the greater the flexibility in controlling memory accessscheduling, for example between the second processor 311 and otherdevices connected to the data communication bus 309. Furthermore, ifmore than one register is used, it is possible to design the MAU and thecontroller of the second processor 311 to schedule and perform memoryreads during periods when the memory is less active.

An embodiment of a data processing apparatus having a memory arbitrationunit which controls write operations to memory from communication busesof different width is shown in FIG. 8.

The data processing apparatus 301 includes a memory 303, a firstprocessor 305, and, optionally, one or additional devices 307 connectedto a first data communication bus 309. The data processing apparatusalso includes a second data processor 311 and, optionally, one or morefurther devices 313 connected to a second data communication bus 315. Inthis embodiment, the first communication bus comprises 32 single bit buslines, and the second communication bus 315 has 192 single bit buslines, although in other embodiments, the first and second datacommunication buses 309, 315 may have any other number of bit lines.

The data processor 301 includes a memory arbitration unit 317, having aplurality of selector switches 351, each having an output port 353 andtwo input ports 357, 359. In this embodiment, each of the 192 single bitbus lines of the second data communication bus 315 maps onto a memoryI/O port 355, and therefore the data processor apparatus includes 192selector switches 351 (only two of which are shown), the output 355 ofeach of which is connected to a respective memory I/O port 355. One ofthe two input ports 357, 359 of each selector switch 351 is connected toa single bit line of the second data communication bus 315.

The first communication bus 309 may be mapped onto the memory I/O portsin any desired configuration. In one embodiment, the first communicationbus 309 is configured to enable byte length words or multiple bytelength words to be written to memory. In one configuration, the 32 bitbus lines are divided into four groups of 8 bus lines, the first groupof eight bus lines being coupled to the first inputs 357 of the firsteight selector switches 351 for input to the first eight I/O ports ofthe memory, the second group of eight bit lines connected to the firstinput port 357 of the second group of eight selector switches 351, forconnection to the next eight memory I/O ports, and so on, so that thethird group of eight bit lines is connected to the third group of eightselector switches, and the fourth group of eight bit lines is connectedto the fourth group of eight selector switches. As there are many moreavailable I/O ports than there are bit lines on the 32 bit bus, the 32bit lines may also be connected to the remaining I/O ports so that thebus has full access to the entire memory. In one embodiment, the firstgroup of eight single bit lines of the first data communication bus 309may be connected to the fifth group of eight selector switches, thesecond group of bit lines connected to the sixth group of eight selectorswitches, and so on, until the 32 bit bus has access to all memory I/Oports.

The selector switches may be controlled to allow 32 bits of data to bewritten to memory in parallel. During a write enable, the other selectorswitches coupled to memory I/O ports to which the memory write is notrequired, are disabled (or masked), so that copies of the same data arenot written to the memory, if this is the intention. The selectorswitches 351 may be enabled in groups of eight by a byte write enablesignal, as shown in Table 1 of FIG. 9. This allows the 32 bit data wordto be divided into eight bit lengths, to allow a user to perform 8, 16and 24 bit write operations. The selector switches may be controlled topermit byte lengths of a word having a length of two bytes or moreeither to be written into contiguous memory segments, or non-contiguousmemory segments. In the embodiment of FIG. 8, in which the second databus has 192 bit lines, masked writes are not required since the buswidth is the same as the width (i.e. number) of memory I/Os.

Modifications and changes to the embodiments disclosed herein will beapparent to those skilled in the art.

1. A data processor apparatus comprising a plurality of processingelements, a memory having a plurality of storage elements arranged in aplurality of columns, a plurality of column decoders, a plurality ofmemory ports coupled to said decoders for at least one outputting datafrom said memory and receiving data for said memory, each of saidplurality of memory ports being couplable to at least a respective oneof said plurality of processor elements such that each processor elementis capable of accessing at least one column of storage elements, adevice for accessing said memory, switch means for switchably couplingeach one of said plurality of memory ports to a respective processingelement and for switchably coupling each one of said plurality of memoryports to said device, and a memory access controller arranged to controlsaid switch means to selectively couple said plurality of memory portsto one of (i) said device and (ii) said plurality of processor elements.2. A data processor apparatus as claimed in claim 1, further comprisinga data bus for coupling said memory ports to said device and furthercomprising a bus decoder for coupling selected memory ports to said databus.
 3. A data processor apparatus as claimed in claim 2, wherein saiddata bus comprises a plurality of bus lines, and said bus decoder isarranged to selectively couple selected memory ports to selected buslines.
 4. A data processor apparatus as claimed in claim 3, wherein thenumber of memory ports is greater than the number of bus lines.
 5. Adata processor apparatus as claimed in claim 2, wherein said data buscomprises a plurality of bus lines, and said bus decoder is arranged toselectively couple selected bus lines to said plurality of memory ports.6. A data processor apparatus as claimed in claim 5, wherein the numberof bus lines is greater than the number of memory ports.
 7. A dataprocessor apparatus as claimed in claim 1, further comprising a data busfor coupling said memory ports to said device, said data bus having aplurality of bus lines wherein the number of bus lines is different tothe number of memory ports, and decoding means between said memory portsand said data bus for one of coupling selected ones of said memory portsto said bus lines, if the number of memory ports exceeds the number ofbus lines, and coupling selected ones of said bus lines to said memoryports, if the number of bus lines exceeds the number of memory ports. 8.A data processor apparatus as claimed in claim 1, wherein saidprocessing elements are arranged to perform operations when saidplurality of memory ports are coupled to said device.
 9. A dataprocessor apparatus as claimed in claim 8, wherein said processingelements are arranged to process data previously read from said memorywhen said plurality of memory ports are coupled to said device.
 10. Adata processor apparatus as claimed in claim 1, further comprising atleast one storage element for storing data received from a memory portbefore being processed by a respective processor element.
 11. A dataprocessor apparatus as claimed in claim 10, comprising at least onerespective storage element coupled to each of said plurality of memoryports for storing data received from said memory ports before beingprocessed by said plurality of processor elements.
 12. A data processorapparatus as claimed in claim 11, comprising two or more storageelements for storing data from each of said plurality of memory portsbefore being processed by said processor elements.
 13. A data processorapparatus as claimed in claim 1 wherein said device comprises aprocessor, a direct memory access (DMA) device or an input/output (I/O)device.
 14. A data processor apparatus as claimed in claim 2, furthercomprising another device coupled to said data bus.
 15. A data processorapparatus as claimed in claim 1, wherein said memory ports each comprisean I/O port.
 16. A data processor apparatus as claimed in claim 1,wherein said memory comprises a random access memory (RAM) and each ofsaid memory ports comprises an input/output (I/O) port of said RAM. 17.A data processor apparatus as claimed in claim 1, wherein each of saidmemory ports comprises a one-bit memory port and further comprising asingle bit line of a parallel data bus between each memory port and arespective processor element for one of read access and write access.18. A data processor apparatus as claimed in claim 2, further comprisingan array controller coupled to said data bus for controlling paralleloperations of said processing elements.
 19. A data processor apparatusas claimed in claim 1, further comprising a data bus for coupling saidmemory ports to said device and an array controller coupled to said databus for controlling parallel operations of said processor elements. 20.A device comprising a memory having a plurality of memory ports for atleast one of outputting data from said memory and receiving data forsaid memory, a data bus having a plurality of bus lines, wherein thenumber of bus lines is different to the number of memory ports, anddecoding means between said memory ports and said data bus for one ofcoupling selected ones of said memory ports to said bus lines, if thenumber of memory ports exceeds the number of bus lines, and couplingselected ones of said bus lines to said memory ports, if the number ofbus lines exceeds the number of memory ports.
 21. A device as claimed inclaim 20, further comprising a processor coupleable to said plurality ofmemory ports, independently of said data bus.
 22. A device as claimed inclaim 21, wherein said processor comprises a plurality of processingelements, each coupleable to a respective memory port.
 23. A device asclaimed in claim 21, further comprising memory access control means forselectively coupling one of said data bus and said processor to saidmemory ports.